diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-05-26 14:44:42 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:35:30 +0000 |
| commit | 0602ce67a6c933662998a0faabb64409fc71a88e (patch) | |
| tree | 0abdfc0145d742b7d1bcec3bdac6ef041bb4b32d /src/northbridge/intel/x4x/x4x.h | |
| parent | b0f1988f893bf5f581917816b11e810309955143 (diff) | |
nb/intel/x4x: Add the option for stacked channel map settings
There seems to be a hardware bug where the combination of non-stacked
channel settings, both channels populated and 533MHz dram speed cause
the display to be unusable.
The code to actually select stacked mode based on hardware
configuration will be add in a followup patch.
This patch does the following:
* Add option to the sysinfo struct for stacked mode
* Fix programming channel 1 DRB which needs special care for the last
populated rank in stacked mode
TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz)
Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/x4x/x4x.h')
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 95f618d1c6..2e9c08ddea 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -340,6 +340,7 @@ struct sysinfo { struct dll_setting dqs_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; struct dll_setting dq_settings[TOTAL_CHANNELS][TOTAL_BYTELANES]; u8 nmode; + u8 stacked_mode; }; #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_WARM_RESET 1 |