nb/intel/x4x: Clarify the raminit memory mapping

This replaces magic values by macros and adds some comments to improve
readability.

Adds a convenient function to fetch the test address of a rank.

Also fixes the temporary memory map by changing a write to MCHBAR
0x100 to 0x110, since this is what vendor does. (No difference
observed thus far)

TESTED on DG43GT

Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

1 files changed, 14 insertions, 6 deletions

diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index 30ec4be2ee..ca66f29154 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -306,9 +306,13 @@ static int calibrate_receive_enable(u8 channel, u8 lane,
 
 void rcven(struct sysinfo *s)
 {
-	int i;
+	int rank;
 	u8 channel, lane, reg8;
-	u32 addr;
+	/*
+	 * Using the macros below the compiler warns about this possibly being
+	 * unitialised.
+	 */
+	u32 addr = 0;
 	struct rec_timing timing[8];
 	u8 mincoarse;
 
@@ -316,11 +320,15 @@ void rcven(struct sysinfo *s)
 	MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc;
 	MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80;
 	FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) {
-		addr = (channel << 29);
 		mincoarse = 0xff;
-		for (i = 0; i < RANKS_PER_CHANNEL &&
-			     !RANK_IS_POPULATED(s->dimms, channel, i); i++)
-			addr += 128 * MiB;
+		/*
+		 * Receive enable calibration happens on the first populated
+		 * rank on each channel.
+		 */
+		FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, channel, rank) {
+			addr = test_address(channel, rank);
+			break;
+		}
 		for (lane = 0; lane < 8; lane++) {
 			printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n",
 				channel, lane, addr);