diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-25 19:54:49 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-24 13:04:47 +0000 |
| commit | 3fa103a60261a3cd1925858a317dc1ffa89797f7 (patch) | |
| tree | 93aa9beb025765eb75e6351ea65480a530fcac95 /src/northbridge/intel/x4x/raminit_tables.c | |
| parent | b4a78045d572d621ec54bd7c061c4b995a1515a7 (diff) | |
nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings
Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x/raminit_tables.c')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_tables.c | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index 47d8a98bee..8ff93c9230 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -288,3 +288,84 @@ const u8 ddr3_emrs1_rtt_nom_config[16][4] = { /* [Config][Rank] */ {0x81, 0x81, 0x81, 0x00}, /* 8D_16S */ {0x81, 0x00, 0x81, 0x00}, /* 16S_16S */ }; + +const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */ + /* 115h[15:0] 117h[23:0] */ + { /* 1N mode */ + { /* DDR3 800MHz */ + {0x0189, 0x000aaa}, /* CAS = 5 */ + {0x0189, 0x101aaa}, /* CAS = 6 */ + }, + { /* DDR3 1067MHz */ + {0x0000, 0x000000}, /* CAS = 5 - Not supported */ + {0x0089, 0x000bbb}, /* CAS = 6 */ + {0x0099, 0x101bbb}, /* CAS = 7 */ + {0x0099, 0x202bbb} /* CAS = 8 */ + },{ /* DDR3 1333 */ + {0x0000, 0x000000}, /* CAS = 5 - Not supported */ + {0x0000, 0x000000}, /* CAS = 6 - Not supported */ + {0x0000, 0x000000}, /* CAS = 7 - Not supported */ + {0x129a, 0x0078dc}, /* CAS = 8 */ + {0x028a, 0x0078dc}, /* CAS = 9 */ + {0x028a, 0x1088dc}, /* CAS = 10 */ + }, + }, + { /* 2N mode */ + { /* DDR3 800MHz */ + {0x0189, 0x000aaa}, /* CAS = 5 */ + {0x0189, 0x101aaa}, /* CAS = 6 */ + {0x0000, 0x000000}, /* CAS = 7 - Not supported */ + {0x0000, 0x000000} /* CAS = 8 - Not suppported */ + }, + { /* DDR3 1067 */ + {0x0000, 0x000000}, /* CAS = 5 - Not supported */ + {0x0089, 0x000bbb}, /* CAS = 6 */ + {0x0099, 0x101bbb}, /* CAS = 7 */ + {0x0099, 0x202bbb} /* CAS = 8 */ + },{ /* DDR3 1333MHz */ + {0x0000, 0x000000}, /* CAS = 5 - Not supported */ + {0x0000, 0x000000}, /* CAS = 6 - Not supported */ + {0x0000, 0x000000}, /* CAS = 7 - Not supported */ + {0x019a, 0x0078dc}, /* CAS = 8 */ + {0x019a, 0x1088dc}, /* CAS = 9 */ + {0x019a, 0x2098dc}, /* CAS = 10 */ + }, + } +}; + +const u8 ddr3_c2_x264[3][6] = { /* [freq][cas] */ + /* DDR3 800MHz */ + {0x78, /* CAS = 5 */ + 0x89}, /* CAS = 6 */ + /* DDR3 1066 */ + {0x00, /* CAS = 5 - Not supported */ + 0xff, /* CAS = 6 */ + 0x8a, /* CAS = 7 */ + 0x9a}, /* CAS = 8 */ + /* DDR3 1333 */ + {0x00, /* CAS = 5 - Not supported */ + 0x00, /* CAS = 6 - Not supported */ + 0xff, /* CAS = 7 - Not supported */ + 0xff, /* CAS = 8 */ + 0xff, /* CAS = 9 */ + 0xff}, /* CAS = 10 */ +}; + +const u16 ddr3_c2_x23c[3][6]={ /* [freq][cas] */ + /* DDR3 800MHz */ + {0x9bbb, /* CAS = 5 */ + 0x8bbb}, /* CAS = 6 */ + /* DDR3 1066MHz */ + {0x0000, /* CAS = 5 - Not supported */ + 0x9baa, /* CAS = 6 */ + 0x8caa, /* CAS = 7 */ + 0x7daa}, /* CAS = 8 */ + + /* DDR3 1333MHz */ + {0x0000, /* CAS = 5 - Not supported */ + 0x0000, /* CAS = 6 - Not supported */ + 0x0000, /* CAS = 7 - Not supported */ + 0xaecb, /* CAS = 8 */ + 0x9fcb, /* CAS = 9 */ + 0x8fcb}, /* CAS = 10 */ +}; |