diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-03 16:01:39 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 22:44:06 +0000 |
| commit | d1c590a66654bdb6be6da85c539c9567be6234a0 (patch) | |
| tree | bee2eebeb8bb5d926c3d4e1402b322e95bd4f0cf /src/northbridge/intel/x4x/raminit.c | |
| parent | 4bc8dfb8207ae13140b3e5b01d3f3e36d66143d6 (diff) | |
nb/intel/x4x: Define and use `HOST_BRIDGE` macro
Other Intel northbridges do this.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change
Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x/raminit.c')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 174e8b501e..9f361b694e 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -122,11 +122,11 @@ static void mchinfo_ddr2(struct sysinfo *s) const u32 eax = cpuid_ext(0x04, 0).eax; printk(BIOS_WARNING, "%d CPU cores\n", ((eax >> 26) & 0x3f) + 1); - u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), 0xe8); + u32 capid = pci_read_config16(HOST_BRIDGE, 0xe8); if (!(capid & (1<<(79-64)))) printk(BIOS_WARNING, "iTPM enabled\n"); - capid = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + capid = pci_read_config32(HOST_BRIDGE, 0xe4); if (!(capid & (1<<(57-32)))) printk(BIOS_WARNING, "ME enabled\n"); @@ -246,7 +246,7 @@ static void select_cas_dramfreq_ddr3(struct sysinfo *s, u32 min_tCLK; u8 try_CAS; - u16 capid = (pci_read_config16(PCI_DEV(0, 0, 0), 0xea) >> 4) & 0x3f; + u16 capid = (pci_read_config16(HOST_BRIDGE, 0xea) >> 4) & 0x3f; switch (s->max_fsb) { default: @@ -344,7 +344,7 @@ static void workaround_stacked_mode(struct sysinfo *s) if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz) return; /* IGD0EN gets disabled if not present before this code runs */ - deven = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + deven = pci_read_config32(HOST_BRIDGE, D0F0_DEVEN); if (deven & IGD0EN) s->stacked_mode = 1; } @@ -593,9 +593,9 @@ static void checkreset_ddr2(int boot_path) pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); /* do magic 0xf0 thing. */ - pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); + pci_and_config8(HOST_BRIDGE, 0xf0, ~(1 << 2)); - pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); + pci_or_config8(HOST_BRIDGE, 0xf0, (1 << 2)); full_reset(); } @@ -616,7 +616,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); - pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff); + pci_write_config8(HOST_BRIDGE, 0xdf, 0xff); memset(&s, 0, sizeof(struct sysinfo)); @@ -671,7 +671,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) checkreset_ddr2(s.boot_path); /* Detect dimms per channel */ - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xe9); + reg8 = pci_read_config8(HOST_BRIDGE, 0xe9); printk(BIOS_DEBUG, "Dimms per channel: %d\n", (reg8 & 0x10) ? 1 : 2); @@ -687,7 +687,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80); - pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1); + pci_or_config8(HOST_BRIDGE, 0xf4, 1); printk(BIOS_DEBUG, "RAM initialization finished.\n"); |