diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-15 10:13:36 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-14 07:40:49 +0000 |
commit | a2cc23169a81f669fa38ebf0f6b1393b06c17fda (patch) | |
tree | 7e728cf410478d6a102e48f2e70a4ea85afdbab8 /src/northbridge/intel/x4x/raminit.c | |
parent | 1848ba3b54dec516471a4a9fce4410ad62918b13 (diff) |
nb/intel/x4x: Rename a things that are not specific to DDR2
This memory controller supports both DDR2 and DDR3 memory, yet many
functions have ddr2 in their name while not being ddr2 specific.
This patch renames those to avoid confusion.
Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x/raminit.c')
-rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 21f7b387bb..efd197f714 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -674,17 +674,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) find_dimm_config(&s); } - switch (s.spd_type) { - case DDR2: - raminit_ddr2(&s, fast_boot); - break; - case DDR3: - // FIXME Add: raminit_ddr3(&s); - break; - default: - die("Unknown DDR type\n"); - break; - } + do_raminit(&s, fast_boot); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80); |