diff options
| author | Damien Zammit <damien@zamaudio.com> | 2016-01-22 22:12:30 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-29 00:27:09 +0100 |
| commit | 5680fafb4d2cdc1d914226ff4d01b9b12ba75097 (patch) | |
| tree | 43e344b201063dfbf03f6c09366ab9383939afed /src/northbridge/intel/x4x/ram_calc.c | |
| parent | 216fc50411a354917cee97b243cdb1dbf1e0a76d (diff) | |
nb/intel/x4x: Move to early cbmem
Previously with errors in the ram init, early cbmem was disabled.
Now that the ram is working correctly, set as early cbmem platform
and update all (1) boards to use it.
Tested on GA-G41M-ES2L
Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13131
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/x4x/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/x4x/ram_calc.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index f11b19a9f1..27562eae83 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ +#include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> #include <arch/io.h> @@ -86,3 +87,9 @@ u8 decode_pciebar(u32 *const base, u32 *const len) *len = max_buses << 20; return 1; } + +void *cbmem_top(void) +{ + u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); + return (void*)(ramtop); +} |