diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-09 01:58:24 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-03-21 20:11:15 +0100 |
| commit | 70a1dda927951e3d3a163ee899f25420f78b56c1 (patch) | |
| tree | c8d9fd3e604526c405d462579654a2901ff40cd1 /src/northbridge/intel/x4x/ram_calc.c | |
| parent | 98adaf5989845f7859054f5cee2cf1f4e0392640 (diff) | |
nb/intel/x4x: Fix issues found by checkpatch.pl
Change-Id: Ie22b8bd5420f8c33df1866410af42ef41ad38362
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18694
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/x4x/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/x4x/ram_calc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 410e3b623a..1009372e31 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -56,7 +56,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) { *base = 0; *len = 0; - const pci_devfn_t dev = PCI_DEV(0,0,0); + const pci_devfn_t dev = PCI_DEV(0, 0, 0); u32 pciexbar = 0; u32 pciexbar_reg; u32 reg32; @@ -98,7 +98,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len) */ void *cbmem_top(void) { - uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); + uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); return (void *) top_of_ram; } |