diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:23:18 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:44 +0000 |
| commit | bbc80f4405a1ba12ad444ef900da6a55d63f45b8 (patch) | |
| tree | 85249be08e8da68f9f7d1aaa5d09454f00febb83 /src/northbridge/intel/x4x/northbridge.c | |
| parent | 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 (diff) | |
nb/intel/x4x: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.
Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 5e46270dc1..de603386c3 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -20,7 +20,6 @@ static void mch_domain_read_resources(struct device *dev) u8 index; u64 tom, touud; u32 tomk, tolud, delta_cbmem; - u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0; const u32 top32memk = 4 * (GiB / KiB); @@ -111,12 +110,7 @@ static void mch_domain_read_resources(struct device *dev) top32memk - (DEFAULT_HECIBAR >> 10), IORESOURCE_RESERVE); - if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - fixed_mem_resource(dev, index++, pcie_config_base >> 10, - pcie_config_size >> 10, IORESOURCE_RESERVE); - } + mmconf_resource(dev, index++); } static void mch_domain_set_resources(struct device *dev) |