nb/intel/x4x: Use SPI flash to cache raminit results

Stores information obtained from decoding dimms and receive enable
results for future use.

Depreciates using rtc nvram to store receive enable settings.

A notable change is that receive enable results are always reused, not
just on a resume from S3.

This requires cbmem to be initialized a bit earlier, right after the
raminit finished to be able to add the sysinfo struct to cbmem which
gets cached to the SPI flash in ramstage.

TESTED on Intel DG43GT with W25Q128.V. With 4 ddr2 dimms time in
raminit goes from 133,857ms (using i2c block read to fetch SPD) to
21,071ms for cached results.

Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 0 insertions, 9 deletions

diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index fbdbcb4496..ab4864b880 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -242,15 +242,6 @@ static void init_dmi(void)
 
 static void x4x_prepare_resume(int s3resume)
 {
-	int cbmem_recovered;
-
-	cbmem_recovered = !cbmem_recovery(s3resume);
-	if (!cbmem_recovered && s3resume) {
-		/* Failed S3 resume, reset to come up cleanly */
-		outb(0x6, 0xcf9);
-		halt();
-	}
-
 	romstage_handoff_init(s3resume);
 }