diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-09 01:58:24 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-03-21 20:11:15 +0100 |
| commit | 70a1dda927951e3d3a163ee899f25420f78b56c1 (patch) | |
| tree | c8d9fd3e604526c405d462579654a2901ff40cd1 /src/northbridge/intel/x4x/early_init.c | |
| parent | 98adaf5989845f7859054f5cee2cf1f4e0392640 (diff) | |
nb/intel/x4x: Fix issues found by checkpatch.pl
Change-Id: Ie22b8bd5420f8c33df1866410af42ef41ad38362
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18694
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/x4x/early_init.c')
| -rw-r--r-- | src/northbridge/intel/x4x/early_init.c | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 7d6afc91ce..a556adca0e 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -40,10 +40,10 @@ void x4x_early_init(void) /* Setup PMBASE */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); /* Setup HECIBAR */ - pci_write_config32(PCI_DEV(0,3,0), 0x10, DEFAULT_HECIBAR); + pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(d0f0, D0F0_PAM(0), 0x30); @@ -116,13 +116,15 @@ static void init_egress(void) EPBAR32(0x20) = reg32; /* Wait for table load */ - while ((EPBAR8(0x26) & (1 << 0)) != 0); + while ((EPBAR8(0x26) & (1 << 0)) != 0) + ; /* VC1: enable */ EPBAR32(0x20) |= 1 << 31; /* Wait for VC1 */ - while ((EPBAR8(0x26) & (1 << 1)) != 0); + while ((EPBAR8(0x26) & (1 << 1)) != 0) + ; printk(BIOS_DEBUG, "Done Egress Port\n"); } @@ -195,10 +197,12 @@ static void init_dmi(void) RCBA32(0x20) |= 1 << 31; /* Wait for VC1 */ - while ((RCBA8(0x26) & (1 << 1)) != 0); + while ((RCBA8(0x26) & (1 << 1)) != 0) + ; /* Wait for table load */ - while ((RCBA8(0x26) & (1 << 0)) != 0); + while ((RCBA8(0x26) & (1 << 0)) != 0) + ; /* ASPM on DMI link */ RCBA16(0x1a8) &= ~0x3; @@ -209,7 +213,8 @@ static void init_dmi(void) /* Set up VC1 max time */ RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000; - while ((DMIBAR32(0x26) & (1 << 1)) != 0); + while ((DMIBAR32(0x26) & (1 << 1)) != 0) + ; printk(BIOS_DEBUG, "Done DMI setup\n"); /* ASPM on DMI */ |