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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-25 18:30:01 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-24 13:03:15 +0000 |
| commit | f1287266ab7587672080aed2ddbc272a95fba9a3 (patch) | |
| tree | ef33cb5bb3d4dfcc684df7411740ec409baff0f3 /src/northbridge/intel/x4x/dq_dqs.c | |
| parent | 9129f1aae9dcd669dfd9a0502d7884261fa324e9 (diff) | |
nb/intel/x4x: Add DDR3 JEDEC init
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs)
This also modifies the send_jedec_cmd function as DDR3 dimms can have
ranks mirrored which needs to be accounted for.
The ddr3_emrs1_config array is placed externally since it is also
needed for write leveling.
Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x/dq_dqs.c')
0 files changed, 0 insertions, 0 deletions