diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-13 12:39:37 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-15 11:21:42 +0000 |
| commit | 9d20c84460093db15445540359e5362bfc914d1a (patch) | |
| tree | 52b4d30dba03594f45026072e06f991b3e575bc0 /src/northbridge/intel/x4x/dq_dqs.c | |
| parent | d26e1cf4849db9c0c8585e17909dd5fcca1977c0 (diff) | |
nb/intel/x4x: Clean up raminit comments
Use C-style comments everywhere, and follow the coding style.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I3ef96c5f6553ad50cee7d7f5614128b62a89e4ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/x4x/dq_dqs.c')
| -rw-r--r-- | src/northbridge/intel/x4x/dq_dqs.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 4362bd6307..82dca44f72 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -278,7 +278,7 @@ int do_write_training(struct sysinfo *s) s->dq_settings[channel][lane] = s->dqs_settings[channel][lane]; } memset(dq_lower, 0, sizeof(dq_lower)); - /* Start from DQS settings */ + /* Start from DQS settings */ memcpy(dq_setting, s->dqs_settings[channel], sizeof(dq_setting)); if (find_dq_limit(s, channel, dq_setting, dq_lower, @@ -525,49 +525,49 @@ static void set_rank_write_level(struct sysinfo *s, u8 channel, u8 config, /* Is shifted by bits 2 later so u8 can be used to reduce size */ static const u8 emrs1_lut[8][4][4] = { /* [Config][Leveling Rank][Rank] */ - { /* Config 0: 2R2R */ + { /* Config 0: 2R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, {0x91, 0x00, 0x11, 0x00}, {0x91, 0x00, 0x00, 0x11} }, - { // Config 1: 2R1R + { /* Config 1: 2R1R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x11, 0x91, 0x00}, {0x91, 0x00, 0x11, 0x00}, {0x00, 0x00, 0x00, 0x00} }, - { // Config 2: 1R2R + { /* Config 2: 1R2R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x91, 0x00, 0x11, 0x00}, {0x91, 0x00, 0x00, 0x11} }, - { // Config 3: 1R1R + { /* Config 3: 1R1R */ {0x11, 0x00, 0x91, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x91, 0x00, 0x11, 0x00}, {0x00, 0x00, 0x00, 0x00} }, - { // Config 4: 2R0R + { /* Config 4: 2R0R */ {0x11, 0x00, 0x00, 0x00}, {0x00, 0x11, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00} }, - { // Config 5: 0R2R + { /* Config 5: 0R2R */ {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x11, 0x00}, {0x00, 0x00, 0x00, 0x11} }, - { // Config 6: 1R0R + { /* Config 6: 1R0R */ {0x11, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00} }, - { // Config 7: 0R1R + { /* Config 7: 0R1R */ {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x11, 0x00}, |