diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:23:18 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:44 +0000 |
| commit | bbc80f4405a1ba12ad444ef900da6a55d63f45b8 (patch) | |
| tree | 85249be08e8da68f9f7d1aaa5d09454f00febb83 /src/northbridge/intel/x4x/bootblock.c | |
| parent | 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 (diff) | |
nb/intel/x4x: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.
Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x/bootblock.c')
| -rw-r--r-- | src/northbridge/intel/x4x/bootblock.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 1192fdb1cb..f15d181354 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -2,15 +2,27 @@ #include <arch/bootblock.h> #include <arch/mmio.h> +#include <assert.h> #include <device/pci_ops.h> +#include <types.h> #include "x4x.h" +static uint32_t encode_pciexbar_length(void) +{ + switch (CONFIG_MMCONF_BUS_NUMBER) { + case 256: return 0 << 1; + case 128: return 1 << 1; + case 64: return 2 << 1; + default: return dead_code_t(uint32_t); + } +} + void bootblock_early_northbridge_init(void) { /* Disable LaGrande Technology (LT) */ read32((void *)TPM_BASE_ADDRESS); - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); } |