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authorDamien Zammit <damien@zamaudio.com>2015-08-19 15:16:59 +1000
committerMartin Roth <martinroth@google.com>2015-12-29 18:03:33 +0100
commit43a1f780ff6809f758092136b0b38c6917c27340 (patch)
treeebb641caf31e477a61addedc46678ba6be4b4889 /src/northbridge/intel/x4x/acpi.c
parente7a336ac29b1ef5aaa1b0aa4926ed75829b491b1 (diff)
northbridge/intel/x4x: Intel 4-series northbridge support
Boots to console on Gigabyte GA-G41M-ES2L Ram initialization *not* included in this patch VGA native init works on analog connector Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/11305 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/x4x/acpi.c')
-rw-r--r--src/northbridge/intel/x4x/acpi.c57
1 files changed, 57 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c
new file mode 100644
index 0000000000..386096c172
--- /dev/null
+++ b/src/northbridge/intel/x4x/acpi.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cbmem.h>
+#include <arch/acpigen.h>
+#include <cpu/cpu.h>
+#include "x4x.h"
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ device_t dev;
+ u32 pciexbar = 0;
+ u32 length = 0;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0,0));
+ if (!decode_pciebar(&pciexbar, &length))
+ return current;
+
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+ pciexbar, 0x0, 0x0, (length >> 20) - 1);
+
+ return current;
+}
+
+unsigned long northbridge_write_acpi_tables(device_t device,
+ unsigned long start,
+ struct acpi_rsdp *rsdp)
+{
+ unsigned long current;
+ current = acpi_align_current(start);
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+
+ return current;
+}