diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-05-15 10:13:36 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-14 07:40:49 +0000 |
| commit | a2cc23169a81f669fa38ebf0f6b1393b06c17fda (patch) | |
| tree | 7e728cf410478d6a102e48f2e70a4ea85afdbab8 /src/northbridge/intel/x4x/Makefile.inc | |
| parent | 1848ba3b54dec516471a4a9fce4410ad62918b13 (diff) | |
nb/intel/x4x: Rename a things that are not specific to DDR2
This memory controller supports both DDR2 and DDR3 memory, yet many
functions have ddr2 in their name while not being ddr2 specific.
This patch renames those to avoid confusion.
Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/x4x/Makefile.inc')
| -rw-r--r-- | src/northbridge/intel/x4x/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 29ece07526..1f7e483f61 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -18,7 +18,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) romstage-y += early_init.c romstage-y += raminit.c -romstage-y += raminit_ddr2.c +romstage-y += raminit_ddr23.c romstage-y += ram_calc.c romstage-y += rcven.c romstage-y += raminit_tables.c |