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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:23:18 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:44 +0000 |
| commit | bbc80f4405a1ba12ad444ef900da6a55d63f45b8 (patch) | |
| tree | 85249be08e8da68f9f7d1aaa5d09454f00febb83 /src/northbridge/intel/x4x/Kconfig | |
| parent | 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 (diff) | |
nb/intel/x4x: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.
Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/x4x/Kconfig')
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index bdef6f2132..32e85d392b 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -25,6 +25,10 @@ config VGA_BIOS_ID config MMCONF_BASE_ADDRESS default 0xe0000000 +config MMCONF_BUS_NUMBER + int + default 256 + config SMM_RESERVED_SIZE hex default 0x100000 |