diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-12-18 11:55:06 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-12-18 11:55:06 +0000 |
| commit | a0360af0f1645d91b139022353f7a3a9f7f85f8a (patch) | |
| tree | e7403be723e727179eed6252fdd5bb920daa9bad /src/northbridge/intel/sch | |
| parent | be61a173512ece32de01562995a91fbbf3f5b335 (diff) | |
A couple of Poulsbo fixes:
- Don't include cmc.bin to the build. It's required, but we don't ship it
- mptable's API changes a bit. Adapt.
- Fix ACPI for new iasl versions with improved code validation
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/sch')
| -rw-r--r-- | src/northbridge/intel/sch/acpi/hostbridge.asl | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl index a029ef524b..7e92a0e671 100644 --- a/src/northbridge/intel/sch/acpi/hostbridge.asl +++ b/src/northbridge/intel/sch/acpi/hostbridge.asl @@ -23,6 +23,9 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI +Name(_ADR, 0) +Name(_BBN, 0) + Device (MCHC) { Name(_ADR, 0x00000000) // 0:0.0 @@ -204,17 +207,17 @@ Method (_CRS, 0, Serialized) 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfebfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00000000,,, TPMR) + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + 0xfec00000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) }) // Find PCI resource area in MCRS |