diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-20 19:41:17 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 12:56:03 +0000 |
| commit | ef90609cbb4229ccc242f67c48a8e14273bf0aac (patch) | |
| tree | bb1ce9a66ee7a0d0458365f284f15a028689816b /src/northbridge/intel/sandybridge | |
| parent | 183ad06f522b279328acb70dfba52d31f9ff9c91 (diff) | |
src: capitalize 'RAM'
Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/memmap.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 6ebd7e0bb6..0784c11313 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -58,12 +58,12 @@ void fill_postcar_frame(struct postcar_frame *pcf) top_of_ram = (uintptr_t)cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of - * ram under 4GiB is the start of the TSEG region. It is required to + * RAM under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems + /* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM |