mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms

Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):

- mrc_cache_load_current: fetches the mrc_cache data and drops it into
  the given buffer.  This is useful for ARM platforms where the mmap
  operation is very expensive.

- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
  given buffer.  This is useful for platforms where the mmap operation
  is a no-op (like x86 platforms).  As the name mentions, we are not
  freeing the memory that we allocated with the mmap, so it is the
  caller's responsibility to do so.

Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot.  This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).

BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
     reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 14 insertions, 11 deletions

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 06b4d1ec45..6d0e845b56 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -297,7 +297,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 	int me_uma_size, cbmem_was_inited, fast_boot, err;
 	ramctr_timing ctrl;
 	spd_raw_data spds[4];
-	struct region_device rdev;
+	size_t mrc_size;
 	ramctr_timing *ctrl_cached = NULL;
 
 	MCHBAR32(SAPMCTL) |= 1;
@@ -324,10 +324,11 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 	early_thermal_init();
 
 	/* Try to find timings in MRC cache */
-	err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev);
-
-	if (!err && !(region_device_sz(&rdev) < sizeof(ctrl)))
-		ctrl_cached = rdev_mmap_full(&rdev);
+	ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+						  MRC_CACHE_VERSION,
+						  &mrc_size);
+	if (mrc_size < sizeof(ctrl))
+		ctrl_cached = NULL;
 
 	/* Before reusing training data, assert that the CPU has not been replaced */
 	if (ctrl_cached && cpuid != ctrl_cached->cpu) {
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index b6b3989790..5e5cc63c38 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -72,8 +72,8 @@ void save_mrc_data(struct pei_data *pei_data)
 
 static void prepare_mrc_cache(struct pei_data *pei_data)
 {
-	struct region_device rdev;
 	u16 c1, c2, checksum, seed_checksum;
+	size_t mrc_size;
 
 	/* Preset just in case there is an error */
 	pei_data->mrc_input = NULL;
@@ -103,16 +103,18 @@ static void prepare_mrc_cache(struct pei_data *pei_data)
 		return;
 	}
 
-	if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) {
+	pei_data->mrc_input = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+							  MRC_CACHE_VERSION,
+							  &mrc_size);
+	if (pei_data->mrc_input == NULL) {
 		/* Error message printed in find_current_mrc_cache */
 		return;
 	}
 
-	pei_data->mrc_input = rdev_mmap_full(&rdev);
-	pei_data->mrc_input_len = region_device_sz(&rdev);
+	pei_data->mrc_input_len = mrc_size;
 
-	printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input,
-			pei_data->mrc_input_len);
+	printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__,
+	       pei_data->mrc_input, mrc_size);
 }
 
 /**