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authorJakub Czapiga <jacz@semihalf.com>2022-02-15 11:50:31 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-08 16:06:33 +0000
commitad6157ebdfddc39b95e388487e00cadd2bbf368b (patch)
treebbb85c9b13faf74515387ee8978eefd6d79e6b06 /src/northbridge/intel/sandybridge
parente96ade6981c60af4d6f24471d7f6a440ab7bfd4e (diff)
timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c4
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index a3e701686f..9082f8a7d3 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -298,7 +298,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
size_t mrc_size;
ramctr_timing *ctrl_cached = NULL;
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
mchbar_setbits32(SAPMCTL, 1 << 0);
@@ -460,7 +460,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
report_memory_config();
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
cbmem_was_inited = !cbmem_recovery(s3resume);
if (!fast_boot)
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index c52203a14e..fbb2b6eebb 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -364,9 +364,9 @@ void perform_raminit(int s3resume)
disable_p2p();
pei_data.boot_mode = s3resume ? 2 : 0;
- timestamp_add_now(TS_BEFORE_INITRAM);
+ timestamp_add_now(TS_INITRAM_START);
sdram_initialize(&pei_data);
- timestamp_add_now(TS_AFTER_INITRAM);
+ timestamp_add_now(TS_INITRAM_END);
/* Sanity check mrc_var location by verifying a known field */
mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE;