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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-04 14:24:23 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-05 22:37:46 +0200 |
| commit | 9ef671769bc5be393f356c85359909a56145a912 (patch) | |
| tree | 892a10d2391b8df86a3841bb07891473b1a1046d /src/northbridge/intel/sandybridge | |
| parent | 1000a5561d0c122e3800896b36767f09f3d96901 (diff) | |
sb/amd/sp5100: Add ehci_async_data_cache CMOS option
SP5100 devices are affected by an erratum that can lock up the
EHCI ports under certain conditions. Add an optional CMOS
option to enable a workaround at the expense of performance.
Change-Id: I305d23dfa50f10a3dcb5c731e8923305c8956dde
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14241
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
0 files changed, 0 insertions, 0 deletions