diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-18 17:49:48 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-06 16:19:01 +0000 |
| commit | 898757fc44e73654c8c093a754356820ea42a355 (patch) | |
| tree | 1ca68cf7b274ff465523d3b9796388f49803b504 /src/northbridge/intel/sandybridge | |
| parent | 1bb327f2162d4ce736a632ef817e48622ae9dbc1 (diff) | |
sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree
Since the PCI bridge in the PCH is always on the same device function,
the device operations can be statically assigned in the devicetree and
there's no need to bind the PCI bridge device operations to the PCI
device during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79169
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chipset.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 15be1b0eb2..9cdb6639b4 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -36,7 +36,7 @@ chip northbridge/intel/sandybridge device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end # PCIe Port #7 device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 - device pci 1e.0 alias pci_bridge off end # PCI bridge + device pci 1e.0 alias pci_bridge off ops bd82x6x_pci_bridge_ops end device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 device pci 1f.3 alias smbus on ops bd82x6x_smbus_ops end |