diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-24 14:48:50 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 17:16:19 +0000 |
| commit | 33232604a71cfb84ef21ff2adc14f4554d1bedb4 (patch) | |
| tree | 7830a72a4eeb74a5adcff6544129bab86acceed1 /src/northbridge/intel/sandybridge | |
| parent | 71693ba43fa8f0d0e7560a3c0a0c465fbd49ce1a (diff) | |
nb/intel: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
4 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 61537e83df..609106f082 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -33,7 +33,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index efe27b1b29..3580f3509d 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -60,7 +60,7 @@ static void sandybridge_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -69,7 +69,7 @@ static void sandybridge_setup_bars(void) printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 635e321c77..3c0b9eccca 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -100,7 +100,7 @@ static void add_fixed_resources(struct device *dev, int index) reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if CONFIG_CHROMEOS_RAMOOPS +#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 09d82d6f81..3f7d1c64ba 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -39,7 +39,7 @@ * MRC scrambler seed offsets should be reserved in * mainboard cmos.layout and not covered by checksum. */ -#if CONFIG_USE_OPTION_TABLE +#if IS_ENABLED(CONFIG_USE_OPTION_TABLE) #include "option_table.h" #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) @@ -236,7 +236,7 @@ void sdram_initialize(struct pei_data *pei_data) die("UEFI PEI System Agent not found.\n"); } -#if CONFIG_USBDEBUG_IN_ROMSTAGE +#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) /* mrc.bin reconfigures USB, so reinit it to have debug */ usbdebug_init(); #endif |