diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-12 13:49:59 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-19 23:01:15 +0000 |
| commit | 2bf28ed63219a6bb76c6e39c8de0e58f4e35e28c (patch) | |
| tree | 800e31e284e0ba4ec643fef6a5dde782e0e6eedc /src/northbridge/intel/sandybridge | |
| parent | e0d38680d4daeeebc2fcc580c23b7305be577ac2 (diff) | |
nb/intel/sandybridge: Clean up MR0 composition
There's no need to use and-masks here.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: If06352daf53ce278dfc64102e023e4f1ea78385c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b5fcc8b865..59dd5be357 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -690,9 +690,6 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; - /* DLL Reset - self clearing - set after CLK frequency has been changed */ - mr0reg = 1 << 8; - /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { mch_cas = (u16) ((ctrl->CAS - 4) << 1); @@ -704,12 +701,15 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) /* Convert tWR to MCH register friendly */ mch_wr = mch_wr_t[ctrl->tWR - 5]; - mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); - mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); - mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); + /* DLL Reset - self clearing - set after CLK frequency has been changed */ + mr0reg = 1 << 8; + + mr0reg |= (mch_cas & 0x1) << 2; + mr0reg |= (mch_cas & 0xe) << 3; + mr0reg |= mch_wr << 9; /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ - mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); + mr0reg |= !is_mobile << 12; return mr0reg; } |