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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-10 19:11:55 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-16 09:37:47 +0000 |
| commit | b8b41338aae9acfa2a49c64d8e57a95653aef610 (patch) | |
| tree | e10e45287667d25754fa7f96ae668b904fc31c12 /src/northbridge/intel/sandybridge | |
| parent | dc0c02fe34fe72b81c0d49879ba342e1125ab535 (diff) | |
nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()
Communicate the RAMOOPS section via ChromeOS GNVS.
Change-Id: I75170e6e34c20db88efa268080d2c38916b31f37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/acpi/sandybridge.asl | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 8 |
2 files changed, 3 insertions, 10 deletions
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 5d7a777803..cf1d61ce9f 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -20,11 +20,6 @@ Device (PDRC) Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif - /* Required for SandyBridge sighting 3715511 */ Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 22743553d9..ead3c67c0d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -14,6 +14,7 @@ #include "chip.h" #include "sandybridge.h" #include <cpu/intel/smm_reloc.h> +#include <vendorcode/google/chromeos/chromeos.h> /* IGD UMA memory */ static uint64_t uma_memory_base = 0; @@ -67,11 +68,8 @@ static void add_fixed_resources(struct device *dev, int index) reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if CONFIG(CHROMEOS_RAMOOPS) - reserved_ram_resource(dev, index++, - CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); -#endif + if (CONFIG(CHROMEOS_RAMOOPS)) + chromeos_reserve_ram_oops(dev, index++); if (is_sandybridge()) { /* Required for SandyBridge sighting 3715511 */ |