diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-08-09 13:44:38 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-07 08:28:28 +0100 |
| commit | 357bb2daf09090192c09ddde501a7e07337614e1 (patch) | |
| tree | aa5b66674f5b94e35a1b4a9d38b73aeb62b6a2ba /src/northbridge/intel/sandybridge | |
| parent | a60ca36c4282c3998d4fc38d55e3dc668017b3ef (diff) | |
SandyBridge/IvyBridge: Use flash map to find MRC cache
Until now, the MRC cache position and size was hard coded in Kconfig.
However, on ChromeOS devices, it should be determined by reading the
FMAP.
This patch provides a minimalistic FMAP parser (libflashmap was too
complex and OS centered) to allow reading the in-ROM flash map and
look for sections.
This will also be needed on some partner devices where coreboot will
have to find the VPD in order to set up the device's mac address
correctly.
The MRC cache implementation demonstrates how to use the FMAP parser.
Change-Id: I34964b72587443a6ca4f27407d778af8728565f8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1701
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 13 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/mrccache.c | 18 |
2 files changed, 16 insertions, 15 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 7dfd10d3ba..229589998f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -44,16 +44,14 @@ config MRC_CACHE_BASE config MRC_CACHE_LOCATION hex + depends on !CHROMEOS default 0x1ec000 config MRC_CACHE_SIZE hex + depends on !CHROMEOS default 0x10000 -config MRC_CACHE_ALIGNMENT - hex - default 0x1000 - config DCACHE_RAM_BASE hex default 0xff7f0000 @@ -85,17 +83,14 @@ config MRC_CACHE_BASE config MRC_CACHE_LOCATION hex + depends on !CHROMEOS default 0x370000 config MRC_CACHE_SIZE hex + depends on !CHROMEOS default 0x10000 -config MRC_CACHE_ALIGNMENT - hex - default 0x1000 - - config DCACHE_RAM_BASE hex default 0xff7e0000 diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 00b3bdd362..2a7727c876 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -28,6 +28,9 @@ #include "sandybridge.h" #include <spi.h> #include <spi_flash.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/fmap.h> +#endif struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache) { @@ -49,18 +52,21 @@ int is_mrc_cache(struct mrc_data_container *mrc_cache) } /* Right now, the offsets for the MRC cache area are hard-coded in the - * northbridge Kconfig. In order to make this more flexible, there are - * a number of options: + * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make + * this more flexible, there are two of options: * - Have each mainboard Kconfig supply a hard-coded offset - * - For ChromeOS devices: implement native FMAP - * - For non-ChromeOS devices: use CBFS + * - Use CBFS */ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - - u32 region_size = CONFIG_MRC_CACHE_SIZE; + u32 region_size; +#if CONFIG_CHROMEOS + region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); +#else + region_size = CONFIG_MRC_CACHE_SIZE; *mrc_region_ptr = (struct mrc_data_container *) (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); +#endif return region_size; } |