diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-02 22:15:03 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-05-21 18:28:01 +0000 |
| commit | 2be59000874eef6829e279ac4f5ec02f35eadf4a (patch) | |
| tree | 10e604a6a6059fee93bef435eb30a2e188d2ccbc /src/northbridge/intel/sandybridge | |
| parent | e7afcd5391ac6cde9f2e8790be7418893228e5a3 (diff) | |
nb/intel/sandybridge: Truncate IOSAV subseq gaps
We set bit 15 of IOSAV_n_SUBSEQ_CTRL three times, but it is reserved.
Since this bitfield is five bits wide, manually truncate the values so
that bit 15 does not get set.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ib61b026b016b0d22e164f8817158ec5093f6bb9e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0f42b6f461..d66a0f0ed3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -854,7 +854,7 @@ void dram_mrscommands(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, IOSAV_ZQCS, 0, - 1, 36, 101, SSQ_NA, + 1, 4, 101, SSQ_NA, 0, 6, 0, slotrank, 0, 0, 0, 0, 31, 0, 0, 0); @@ -1976,7 +1976,7 @@ int write_training(ramctr_timing *ctrl) /* DRAM command ZQCS */ IOSAV_SUBSEQUENCE(channel, 0, IOSAV_ZQCS, 0, - 1, 36, 101, SSQ_NA, + 1, 4, 101, SSQ_NA, 0, 6, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0); @@ -2935,7 +2935,7 @@ int channel_test(ramctr_timing *ctrl) /* DRAM command ACT */ IOSAV_SUBSEQUENCE(channel, 0, IOSAV_ACT, 1, - 4, 40, 40, SSQ_NA, + 4, 8, 40, SSQ_NA, 0, 6, 0, slotrank, 0, 0, 1, 0, 18, 0, 0, 0); |