diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-06-09 18:13:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:48:44 +0200 |
| commit | 266a1f794dc28053e97794cbeb3f1a588137698b (patch) | |
| tree | 7cb11796fa351bd50d15af6be9508a15be223192 /src/northbridge/intel/sandybridge | |
| parent | e7f35cd2924de7c9b2e8a74a50d35928b9da76a4 (diff) | |
nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chip.h | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 21 |
2 files changed, 25 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 5effc0da95..d002824287 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -47,6 +47,11 @@ struct northbridge_intel_sandybridge_config { u16 max_mem_clock_mhz; struct i915_gpu_controller_info gfx; + + /* + * Maximum PCI mmio size in MiB. + */ + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6bb77b2c6a..4563547c79 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -204,6 +204,7 @@ typedef struct ramctr_timing_st { #define GET_ERR_CHANNEL(x) (x>>16) static void program_timings(ramctr_timing * ctrl, int channel); +static unsigned int get_mmio_size(void); static const char *ecc_decoder[] = { "inactive", @@ -1086,7 +1087,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) size_t tsegbasedelta, remapbase, remaplimit; uint16_t ggc; - mmiosize = 0x400; + mmiosize = get_mmio_size(); ggc = pci_read_config16(NORTHBRIDGE, GGC); if (!(ggc & 2)) { @@ -4384,6 +4385,24 @@ static unsigned int get_mem_min_tck(void) } } +#define DEFAULT_PCI_MMIO_SIZE 2048 + +static unsigned int get_mmio_size(void) +{ + const struct device *dev; + const struct northbridge_intel_sandybridge_config *cfg = NULL; + + dev = dev_find_slot(0, HOST_BRIDGE); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + return DEFAULT_PCI_MMIO_SIZE; + else + return cfg->pci_mmio_size; +} + void perform_raminit(int s3resume) { spd_raw_data spd[4]; |