summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/sandybridge
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2022-11-07 08:47:33 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-11-30 15:58:19 +0000
commitfade723b2551d12c98c91c968d213eeb827d856d (patch)
treef504f6adce43761ac9cb76498279fea0686074be /src/northbridge/intel/sandybridge
parent691d58f9996d2ff3820b2c08646e98f16bbde2ee (diff)
nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
-rw-r--r--src/northbridge/intel/sandybridge/chipset.cb2
-rw-r--r--src/northbridge/intel/sandybridge/northbridge.c15
2 files changed, 4 insertions, 13 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb
index ae02a5b927..e7ade1977e 100644
--- a/src/northbridge/intel/sandybridge/chipset.cb
+++ b/src/northbridge/intel/sandybridge/chipset.cb
@@ -2,6 +2,7 @@
chip northbridge/intel/sandybridge
device cpu_cluster 0 on
+ ops sandybridge_cpu_bus_ops
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
@@ -14,5 +15,6 @@ chip northbridge/intel/sandybridge
end
device domain 0 on
+ ops sandybridge_pci_domain_ops
end
end
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 521044bcba..ad85d68cdc 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -52,7 +52,7 @@ static const char *northbridge_acpi_name(const struct device *dev)
return NULL;
}
-static struct device_operations pci_domain_ops = {
+struct device_operations sandybridge_pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus,
@@ -412,23 +412,12 @@ static const struct pci_driver mc_driver __pci_driver = {
.devices = pci_device_ids,
};
-static struct device_operations cpu_bus_ops = {
+struct device_operations sandybridge_cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.init = mp_cpu_bus_init,
};
-static void enable_dev(struct device *dev)
-{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
struct chip_operations northbridge_intel_sandybridge_ops = {
CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge")
- .enable_dev = enable_dev,
};