diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-14 01:31:15 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-22 20:32:15 +0000 |
| commit | 068c2595f2a3cc57d73849926f420bd6f63d72f6 (patch) | |
| tree | f57d0ef46699373b1b98689312ac26a0acf57f16 /src/northbridge/intel/sandybridge | |
| parent | 7f5a97ce98120561dff449cbbf9f953bd9b6d623 (diff) | |
nb/intel/sandybridge: Run `read_mpr_training` before write training
Reference code does this, so follow suit.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I21c5161da55b380dd4b2d574b22a1ef038f55fce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index e0b5a3dfc2..ae9a4f46fa 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -684,16 +684,16 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ if (err) return err; - err = write_training(ctrl); + err = read_mpr_training(ctrl); if (err) return err; - printram("CP5a\n"); - - err = read_mpr_training(ctrl); + err = write_training(ctrl); if (err) return err; + printram("CP5a\n"); + printram("CP5b\n"); err = command_training(ctrl); |