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authorStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-04 00:08:51 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-05 20:59:31 +0200
commit00636b0daefc3c499990744226a0e1a316d71731 (patch)
tree4360fe7a5817a4d6c2164daf547b7d9ba5bd46a8 /src/northbridge/intel/sandybridge/udelay.c
parent4dd3853437a3506880e2879e6640d455778f6413 (diff)
Add support for Intel Sandybridge CPU (northbridge part)
Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/udelay.c')
-rw-r--r--src/northbridge/intel/sandybridge/udelay.c58
1 files changed, 58 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
new file mode 100644
index 0000000000..3d8ba96d75
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+ u32 dword;
+ tsc_t tsc, tsc1, tscd;
+ msr_t msr;
+ u32 fsb = 100, divisor;
+ u32 d; /* ticks per us */
+ u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */
+
+ msr = rdmsr(0xce);
+ divisor = (msr.lo >> 8) & 0xff;
+
+ d = fsb * divisor;
+
+ tscd.hi = us / dn;
+ tscd.lo = (us - tscd.hi * dn) * d;
+
+ tsc1 = rdtsc();
+ dword = tsc1.lo + tscd.lo;
+ if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+ tsc1.hi++;
+ }
+ tsc1.lo = dword;
+ tsc1.hi += tscd.hi;
+
+ do {
+ tsc = rdtsc();
+ } while ((tsc.hi < tsc1.hi)
+ || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
+}