diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-07 13:11:17 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-12 14:34:56 +0000 |
| commit | 964d91f7d745ee71b2e7f3ffb90aa8fe7a373704 (patch) | |
| tree | d79581c140f66071060fd126e2c37819eceed77c /src/northbridge/intel/sandybridge/sandybridge.h | |
| parent | 927b1c01611663545da6d2d9048ce1f37bc04dcf (diff) | |
nb/intel/sandybridge: Clean up stepping logic
Do not combine the host bridge device ID with the CPU stepping because
it is confusing. Although Sandy/Ivy Bridge processors incorporate both
CPU and northbridge components into the same die, it is best to treat
them separately. Plus, this change enables moving CPU stepping macros
from northbridge code into the CPU scope, which is done in a follow-up.
Change-Id: I27ad609eb53b96987ad5445301b5392055fa4ea1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/sandybridge.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8f9d118288..e5f2132ab8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -9,22 +9,22 @@ #define BASE_REV_MASK 0x50 /* SandyBridge CPU stepping */ -#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ -#define SNB_STEP_D1 (BASE_REV_SNB + 6) -#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ +#define SNB_STEP_D0 5 /* Also J0 */ +#define SNB_STEP_D1 6 +#define SNB_STEP_D2 7 /* Also J1/Q0 */ /* IvyBridge CPU stepping */ -#define IVB_STEP_A0 (BASE_REV_IVB + 0) -#define IVB_STEP_B0 (BASE_REV_IVB + 2) -#define IVB_STEP_C0 (BASE_REV_IVB + 4) -#define IVB_STEP_K0 (BASE_REV_IVB + 5) -#define IVB_STEP_D0 (BASE_REV_IVB + 6) +#define IVB_STEP_A0 0 +#define IVB_STEP_B0 2 +#define IVB_STEP_C0 4 +#define IVB_STEP_K0 5 +#define IVB_STEP_D0 6 #include "memmap.h" /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include <stdint.h> +#include <types.h> /* Chipset types */ enum platform_type { @@ -87,8 +87,9 @@ enum platform_type { #ifndef __ASSEMBLER__ +bool is_sandybridge(void); + void intel_sandybridge_finalize_smm(void); -int bridge_silicon_revision(void); void systemagent_early_init(void); void sandybridge_init_iommu(void); void sandybridge_late_initialization(void); |