diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-01-26 20:02:14 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-02 21:46:49 +0100 |
| commit | 9f3f9154c9f3dd1e3cfbd2703b681c3e9ddf4dc7 (patch) | |
| tree | c473e23fc7dc436629f0ca444ccf113173f632e4 /src/northbridge/intel/sandybridge/sandybridge.h | |
| parent | 2bdeb7f843c707023ea2bd39e314f8eec51c7add (diff) | |
nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
Instead of hardcoding the maximum supported DDR frequency to
800Mhz (DDR3-1600), read the fuse bits that encode this information.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/sandybridge.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 570e1f7864..ba8f8d9ae7 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -99,6 +99,9 @@ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ +#define CAPID0_A 0xe4 /* Capabilities Register A */ +#define CAPID0_B 0xe8 /* Capabilities Register B */ + #define SKPAD 0xdc /* Scratchpad Data */ /* Device 0:1.0 PCI configuration space (PCI Express) */ |