diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-02-05 19:08:03 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 09:30:21 +0000 |
| commit | 67031a565b3179fa5a28282fc2e24b47d16003e8 (patch) | |
| tree | d56eaf320fcdc2b2940a24d77c20077fb970951c /src/northbridge/intel/sandybridge/sandybridge.h | |
| parent | 64f0bcb6b0c4ee0fb55e6e600a48a1c61d2e97ef (diff) | |
cpu/intel/sandybridge: Put stage cache into TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
The code is mostly copied from src/cpu/intel/haswell.
TESTED on Thinkpad X220: on a cold boot the stage cache gets created
and on S3 the cached ramstage gets properly used.
Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/sandybridge.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index a3b4faad1d..46ebfc3df0 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -40,7 +40,8 @@ #define IVB_STEP_D0 (BASE_REV_IVB + 6) /* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 + +#define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ |