diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 19:11:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:48:35 +0000 |
| commit | fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch) | |
| tree | af8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/northbridge/intel/sandybridge/romstage.c | |
| parent | 59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff) | |
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index c76d2f4f4a..079e1b13ba 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -63,17 +63,11 @@ void mainboard_romstage_entry(void) /* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init(); - /* Initialize superio */ - mainboard_config_superio(); - /* USB is initialized in MRC if MRC is used. */ if (CONFIG(USE_NATIVE_RAMINIT)) { early_usb_init(mainboard_usb_ports); } - /* Initialize console device(s) */ - console_init(); - /* Perform some early chipset initialization required * before RAM initialization can work */ |