diff options
| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-02-27 22:18:11 +0100 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-07-25 15:53:35 +0000 |
| commit | db70f3bb4d5d58441b1c93d216347ec296b4f787 (patch) | |
| tree | dfa44a3dc22d53f39d364b15c2f56792e0ef7115 /src/northbridge/intel/sandybridge/romstage.c | |
| parent | b009ac49c85161ea2746f8bdfc6ce28a8f46e8bc (diff) | |
drivers/tpm: Add TPM ramstage driver for devices without vboot.
Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 3bfefb9fc7..3e128cdff3 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,7 +28,6 @@ #include <device/pci_def.h> #include <device/device.h> #include <halt.h> -#include <security/tpm/tspi.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> @@ -117,8 +116,5 @@ void mainboard_romstage_entry(unsigned long bist) northbridge_romstage_finalize(s3resume); - if (IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) - tpm_setup(s3resume); - post_code(0x3f); } |