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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-17 20:43:04 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-23 02:36:36 +0000 |
| commit | b33c6fbfd5f9050686b97f2fe3e4b94862a96a74 (patch) | |
| tree | 7ec3112b4bf33b25c3a200dee28394f1cce11aa2 /src/northbridge/intel/sandybridge/romstage.c | |
| parent | 4ce0a07f0670e74dd22d5f7af4b8603db2320ded (diff) | |
nb/intel/x4x,sandybridge: Move INITRAM timestamps
Let's not have CBMEM hooks in between the different
INITRAM timestamps.
Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index fad8e2f91a..49f334e397 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -5,7 +5,6 @@ #include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <romstage_handoff.h> -#include <timestamp.h> #include "sandybridge.h" #include <arch/romstage.h> #include <device/pci_def.h> @@ -63,8 +62,6 @@ void mainboard_romstage_entry(void) perform_raminit(s3resume); - timestamp_add_now(TS_AFTER_INITRAM); - post_code(0x3b); /* Perform some initialization that must run before stage2 */ early_pch_reset_pmcon(); |