aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/intel/sandybridge/romstage.c
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-11-12 16:42:33 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:46:26 +0000
commit9c538348d8ccaef2c3dd6b898a1f44b00ea59690 (patch)
tree79eac3af79546b14b110b059e31eb18d33de4ce0 /src/northbridge/intel/sandybridge/romstage.c
parent934b8da442a04978c6320299c616d3e8f05cb731 (diff)
nb/intel/sandybridge: Make the mainboard_rcba_config hook optional
This also changes the name to mainboard_late_rcba_config to better reflect what it does. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 92882b4b61..c76d2f4f4a 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -34,6 +34,10 @@ __weak void mainboard_early_init(int s3_resume)
{
}
+__weak void mainboard_late_rcba_config(void)
+{
+}
+
static void early_pch_reset_pmcon(void)
{
u8 reg8;
@@ -100,7 +104,7 @@ void mainboard_romstage_entry(void)
southbridge_configure_default_intmap();
southbridge_rcba_config();
- mainboard_rcba_config();
+ mainboard_late_rcba_config();
post_code(0x3d);