diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 19:23:03 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-09 00:32:28 +0000 |
| commit | 9733f6a33687547a9a38589468a2b7b2b927461f (patch) | |
| tree | c13a4ee4536f88ac3b21cdd6ef1cce3d36cdfb90 /src/northbridge/intel/sandybridge/romstage.c | |
| parent | 8ad0a4c0b88718a0b0ba4ba934ff526fe6875702 (diff) | |
nb/intel/sandybridge: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index dce024b033..b9841b5408 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -25,12 +25,8 @@ __weak void mainboard_late_rcba_config(void) static void early_pch_reset_pmcon(void) { - u8 reg8; - /* Reset RTC power status */ - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); + pci_and_config8(PCH_LPC_DEV, GEN_PMCON_3, ~(1 << 2)); } /* The romstage entry point for this platform is not mainboard-specific, hence the name */ |