diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-25 09:53:23 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-13 09:29:33 +0000 |
| commit | 9005071c5fb1d75b2a54aa0b3e7af47e25d2de54 (patch) | |
| tree | 507bada945aaf0c67dbe0dcbb823c97b569be4f4 /src/northbridge/intel/sandybridge/romstage.c | |
| parent | 5709e03613b342f9dc00a659b6474c6ee510fcc3 (diff) | |
nb/intel/sandybridge: Move boot_count_increment()
Move boot_count_increment() to romstage.c, drop preprocessor code and
only increase counter once on regular boot.
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.
Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32067
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 43316a2f22..064d042e56 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -30,6 +30,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> +#include <elog.h> static void early_pch_reset_pmcon(void) { @@ -79,6 +80,9 @@ void mainboard_romstage_entry(unsigned long bist) s3resume = southbridge_detect_s3_resume(); + if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) + boot_count_increment(); + post_code(0x38); mainboard_early_init(s3resume); |