diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2017-05-03 17:47:54 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-05 23:21:32 +0200 |
| commit | 5c31af8e1afd31c30deb33f65ca3b712b0553552 (patch) | |
| tree | 5b40f5f54305858c7d4458594796e50737d0006a /src/northbridge/intel/sandybridge/romstage.c | |
| parent | c9026b2945832a4d3566be5e06221874cdb53738 (diff) | |
nb/intel/sandybridge/romstage: Use register name
Use register name instead of hex value.
No functional change.
Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 738e2851af..8608d5a8a4 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -38,9 +38,9 @@ static void early_pch_init(void) u8 reg8; // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); } /* Platform has no romstage entry point under mainboard directory, |