diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-05-05 16:29:41 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 15:52:01 +0000 |
| commit | 1bc7b6e1350c4ba8eee10a859d10150b15b7b7e9 (patch) | |
| tree | 1751b8ebc3e6b6657d41d1b92e3e070fa8c8bb3e /src/northbridge/intel/sandybridge/romstage.c | |
| parent | ba092a9ab6e87fec458d6557d0114147e2713686 (diff) | |
{gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function
Use already defined system_reset() and full_reset() functions.
Change-Id: Ic29fab70cf7f23d49c3eeeb97c984c523f973972
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/romstage.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 3fab3be85d..43316a2f22 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <console/console.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <timestamp.h> @@ -47,10 +48,8 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; - if (MCHBAR16(SSKPD) == 0xCAFE) { - outb(0x6, 0xcf9); - halt (); - } + if (MCHBAR16(SSKPD) == 0xCAFE) + system_reset(); if (bist == 0) enable_lapic(); |