nb/intel/sandybridge: Deduplicate report_memory_config

Use the version from native raminit, as it takes the reference clock
into account.

Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 68 insertions, 0 deletions

diff --git a/src/northbridge/intel/sandybridge/raminit_shared.c b/src/northbridge/intel/sandybridge/raminit_shared.c
new file mode 100644
index 0000000000..6162544bdc
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/raminit_shared.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <types.h>
+
+#include "sandybridge.h"
+
+static const char *const ecc_decoder[] = {
+	"inactive",
+	"active on IO",
+	"disabled on IO",
+	"active",
+};
+
+#define ON_OFF(val) (((val) & 1) ? "on" : "off")
+
+/* Print the memory controller configuration as read from the memory controller registers. */
+void report_memory_config(void)
+{
+	u32 addr_decoder_common, addr_decode_ch[2];
+	int i;
+
+	addr_decoder_common = MCHBAR32(MAD_CHNL);
+	addr_decode_ch[0]   = MCHBAR32(MAD_DIMM_CH0);
+	addr_decode_ch[1]   = MCHBAR32(MAD_DIMM_CH1);
+
+	const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
+
+	printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk);
+	printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
+	       (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100);
+
+	printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
+	       (addr_decoder_common >> 0) & 3,
+	       (addr_decoder_common >> 2) & 3,
+	       (addr_decoder_common >> 4) & 3);
+
+	for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+		u32 ch_conf = addr_decode_ch[i];
+		printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+		printk(BIOS_DEBUG, "   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+		printk(BIOS_DEBUG, "   enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22));
+		printk(BIOS_DEBUG, "   rank interleave %s\n", ON_OFF(ch_conf >> 21));
+		printk(BIOS_DEBUG, "   DIMMA %d MB width x%d %s rank%s\n",
+		       ((ch_conf >>  0) & 0xff) * 256,
+		       ((ch_conf >> 19) & 1) ? 16 : 8,
+		       ((ch_conf >> 17) & 1) ? "dual" : "single",
+		       ((ch_conf >> 16) & 1) ? "" : ", selected");
+		printk(BIOS_DEBUG, "   DIMMB %d MB width x%d %s rank%s\n",
+		       ((ch_conf >>  8) & 0xff) * 256,
+		       ((ch_conf >> 20) & 1) ? 16 : 8,
+		       ((ch_conf >> 18) & 1) ? "dual" : "single",
+		       ((ch_conf >> 16) & 1) ? ", selected" : "");
+	}
+}
+#undef ON_OFF