diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 19:01:28 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-16 12:06:53 +0000 |
| commit | 71902014e33d641ac2481a7e1f7670fee6a78a25 (patch) | |
| tree | 6fb445a5e7a603a3451b04b957a8c3a7ed69de90 /src/northbridge/intel/sandybridge/raminit_native.c | |
| parent | 2f3cc0035dd29c0d63aa8a32876c84256304b210 (diff) | |
nb/intel/sandybridge: Drop write_controller_mr() function
The only reason to write the MR values to the training result registers
is for EV (Electrical Validation) usage. The hardware doesn't need it.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I808174494729453f4ebcaa13258d735faae68d72
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_native.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 844e69af3b..53017eb8c2 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -715,8 +715,6 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ set_read_write_timings(ctrl); - write_controller_mr(ctrl); - if (!s3resume) { err = channel_test(ctrl); if (err) |