diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-07 12:34:36 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-23 16:11:35 +0000 |
| commit | 9f4ed3b5504e564c44f14dce0bab0f9bc92779b6 (patch) | |
| tree | 14425d8a41aeb93b6d4e12c9f312ff96c79dd8e1 /src/northbridge/intel/sandybridge/raminit_common.h | |
| parent | a853e7acdba6b58e2efb57e186ae0d14ea85fad2 (diff) | |
nb/intel/sandybridge: Always wait for IOSAV after starting it
Ensure that IOSAV is finished before continuing. This might solve some
random failures on the I/O and roundtrip latency training algorithm.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ic08a40346b6c60e372bada10f9c4ee42eb974f9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48403
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 3de29ffde6..53d0cd94ef 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -291,7 +291,6 @@ typedef struct ramctr_timing_st ramctr_timing; void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); -void iosav_run_once(const int ch); void wait_for_iosav(int channel); void iosav_run_once_and_wait(const int ch); |