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authorAngel Pons <th3fanbus@gmail.com>2020-03-24 11:12:09 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-04-19 09:46:42 +0000
commitfc9302465ba1e78f9a99440e1898b3714861290d (patch)
treef7d827b75cccc6eeee34ead5c0ac2e874dfac541 /src/northbridge/intel/sandybridge/raminit_common.h
parent64ba44f7fb7a64c5cc1e9155758b57589320b1a5 (diff)
nb/intel/sandybridge: Refactor get_mem_min_tck
It is not necessary to pass its value around various function calls. Move it closer to where it is actually used, so as to make it static. Also, use config_of_soc and flip the branches of the first conditional. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.h')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 93541b50fd..314c67de80 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -174,7 +174,6 @@ void dram_timing_regs(ramctr_timing *ctrl);
void dram_dimm_mapping(ramctr_timing *ctrl);
void dram_dimm_set_mapping(ramctr_timing *ctrl, int training);
void dram_zones(ramctr_timing *ctrl, int training);
-unsigned int get_mem_min_tck(void);
void dram_memorymap(ramctr_timing *ctrl, int me_uma_size);
void dram_jedecreset(ramctr_timing *ctrl);
int read_training(ramctr_timing *ctrl);