diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-03-21 13:23:32 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-23 19:28:14 +0000 |
commit | 89ae6b8fc2901b56dd1839a2d569493ce668a32c (patch) | |
tree | 7b537bbf2c38c56cff18f38b85f86b52a7c1da04 /src/northbridge/intel/sandybridge/raminit_common.h | |
parent | a6a64183d6c5d535df5e62fad419402cd896f03d (diff) |
nb/intel/sandybridge: Use cached CPUID
Now that we have it, we might as well pass it around.
Tested on Asus P8Z77-V LX2, still boots fine.
Change-Id: Ia5aa2f932321983f11d2f8869aa624832afe9347
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39721
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.h')
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 0cbac8ae20..0ff9265052 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -181,7 +181,7 @@ void normalize_training(ramctr_timing *ctrl); void write_controller_mr(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); -void set_wmm_behavior(void); +void set_wmm_behavior(const u32 cpu); void prepare_training(ramctr_timing *ctrl); void set_read_write_timings(ramctr_timing *ctrl); void set_normal_operation(ramctr_timing *ctrl); |