nb/intel/sandybridge: Clean up COMPOFST1 logic

This register needs to be updated differently depending on the CPU
generation and stepping. Handle this as per reference code. Further,
introduce a bitfield for the register to make the code easier to read.

Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 17 insertions, 0 deletions

diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index f2d0fb5060..debfaa2f2a 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -140,6 +140,23 @@ union gdcr_training_mod_reg {
 	u32 raw;
 };
 
+union comp_ofst_1_reg {
+	struct {
+		u32 dq_odt_down  : 3; /* [ 2.. 0] */
+		u32 dq_odt_up    : 3; /* [ 5.. 3] */
+		u32 clk_odt_down : 3; /* [ 8.. 6] */
+		u32 clk_odt_up   : 3; /* [11.. 9] */
+		u32 dq_drv_down  : 3; /* [14..12] */
+		u32 dq_drv_up    : 3; /* [17..15] */
+		u32 clk_drv_down : 3; /* [20..18] */
+		u32 clk_drv_up   : 3; /* [23..21] */
+		u32 ctl_drv_down : 3; /* [26..24] */
+		u32 ctl_drv_up   : 3; /* [29..27] */
+		u32              : 2;
+	};
+	u32 raw;
+};
+
 union tc_dbp_reg {
 	struct {
 		u32 tRCD : 4; /* [ 3.. 0] */