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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-15 12:50:03 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-22 20:41:08 +0000 |
| commit | a1f1714ca5bcef864d154676b48fc30fa459f8dc (patch) | |
| tree | 8682be211361e9eda5e3d842e5e04ad9d6425f36 /src/northbridge/intel/sandybridge/raminit_common.c | |
| parent | 820bce7322d2af612a39c94c3391b317e33adfb8 (diff) | |
nb/intel/sandybridge: Clarify register write
It is necessary to program this register before doing an I/O reset.
Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index ef4ae455f8..0939fe6348 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1954,6 +1954,7 @@ static int jedec_write_leveling(ramctr_timing *ctrl) write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); + /* Needs to be programmed before I/O reset below */ const union gdcr_training_mod_reg training_mod = { .write_leveling_mode = 1, .enable_dqs_wl = 5, |