diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 19:55:51 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-22 19:22:15 +0000 |
| commit | 593f4ca10b8ce8e859b9ec23412154bce8850e63 (patch) | |
| tree | 3b7f09e5b1e4bf3ace91188d47b5402ad1dacd7f /src/northbridge/intel/sandybridge/raminit_common.c | |
| parent | 59996e03774e5430bd94a8a0eb51a927a1ef4eb1 (diff) | |
nb/intel/sandybridge: Clean up TC_OTHP writes
ODT stretch is configured for both slots in `dram_odt_stretch`. Also
drop an unjustified OR, which is setting ODT stretch for one slot.
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47490
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 92d0c4f47d..a48a84f58b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -142,7 +142,7 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) void dram_timing_regs(ramctr_timing *ctrl) { - u32 reg, addr, val32; + u32 reg, val32; int channel; FOR_ALL_CHANNELS { @@ -169,14 +169,13 @@ void dram_timing_regs(ramctr_timing *ctrl) MCHBAR32(TC_RAP_ch(channel)) = reg; /* Other parameters */ - addr = TC_OTHP_ch(channel); reg = 0; reg |= (ctrl->tXPDLL << 0); reg |= (ctrl->tXP << 5); reg |= (ctrl->tAONPD << 8); reg |= 0xa0000; - printram("OTHP [%x] = %x\n", addr, reg); - MCHBAR32(addr) = reg; + printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), reg); + MCHBAR32(TC_OTHP_ch(channel)) = reg; /* Debug parameters - only applies to Ivy Bridge */ if (IS_IVY_CPU(ctrl->cpu)) { @@ -195,8 +194,6 @@ void dram_timing_regs(ramctr_timing *ctrl) MCHBAR32(TC_DTP_ch(channel)) = reg; } - MCHBAR32_OR(addr, 0x00020000); - dram_odt_stretch(ctrl, channel); /* |